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| HV1816 8-Channel High Voltage Analog Switch Ordering Information Package Options VPP +80V VNN -80V VSIG 130VP-P 28-pin Plastic DIP HV1816P 28-lead Plastic Chip Carrier HV1816PJ Die HV1816X Features s HVCMOS(R) technology s Up to 130V peak to peak output switching s Output On-resistance typically 40 ohms s Low parasitic capacitances www..com General Description Not recommended for new designs. Please use HV202 instead. This device is an 8-channel high-voltage integrated circuit (HVIC) intended for use in applications requiring high voltage switching controlled by low voltage signals; e.g., ultrasound imaging and printers. Input data is shifted into an 8-bit shift register which can then be retained in an 8-bit latch. Using HVCMOS technology, this HVIC combines high voltage bilateral DMOS switches and low power CMOS logic to provide efficient control of high voltage analog signals. s DC to 10MHz analog signal frequency s -45dB typical output off isolation at 5MHz s CMOS logic circuitry for low power and excellent noise immunity s On-chip shift register, latch and clear logic circuitry 13 Absolute Maximum Ratings* VDD Logic power supply voltage VPP - VNN supply voltage VPP Positive high voltage supply VNN Negative high voltage supply Logic input voltages Analog signal range Peak analog signal current/channel Storage temperature Power dissipation -0.5V to +18V 174V -0.5V to +90V +0.5V to -90V -0.5V to VDD +0.3V VNN to VPP 1.5A -65C to +150C 1.2W * Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. 13-17 HV1816 Electrical Characteristics (over operating conditions, VPP = +80V, VNN = -80V and VDD = 15V unless otherwise noted) DC Characteristics Characteristics Switch (ON) Resistance Switch (ON) Resistance Switch (ON) Resistance Switch (ON) Resistance Switch (ON) Resistance Matching Switch Off Leakage Per Switch DC Offset Switch Off DC Offset Switch On Pole to Pole Switch Capacitance Logic Input Capacitance Pos. HV Supply Current Neg. HV Supply Current Pos. HV Supply Current Neg. HV Supply Current Pos. HV Supply Current www..com Sym RONS RONS RONS RONS RONS ISOL 0C min max 50 35 55 40 15 50 500 500 min +25C typ 40 25 45 25 max 50 35 55 40 15 0.5 100 100 4.5 3.5 50 500 500 10 +70C min max 60 45 65 50 15 150 500 500 10 Units ohms ohms ohms ohms % A mV mV pF pF Test Conditions ISW = 5mA, VSIG = 0V ISW = 200mA, VSIG = 0V VPP = +50V, VNN = -50V ISW = 5mA, VSIG = 0V VPP = +50V, VNN = -50V ISW = 200mA, VSIG = 0V VPP = +50V, VNN = -50V ISW = 5mA, VSIG = 0V VSIG = VPP -10V thru 10K with 8 SWS in parallel RL = 100K RL = 100K DC Bias = 40V f = 1MHz ALL SWS OFF 1 SW ON, ISW = 5mA VSIG = 0V VPP = +50V, VNN = -50V, 1 SW ON, ISW = 5mA VSIG 0.1% Duty Cycle, f = 10KHz fCLK = 3MHz CSW CIN IPPQ INNQ IPPQ INNQ IPPQ INNQ 10 200 -200 50 -50 0.8 -0.8 0.6 -0.6 1.5 200 -200 1.6 -1.6 1.2 -1.2 200 -200 A A mA mA mA mA A Neg. HV Supply Current Switch Output Peak Current Logic Supply Average Current Logic Supply Quiescent Current Data Out Source Current Data Out Sink Current IDD IDDQ ISOR ISINK 0.7 0.7 0.8 0.8 4 10 0.9 0.9 6 500 0.7 0.7 mA A mA mA VOUT = VDD - 0.7V VOUT = 0.7V AC Characteristics Characteristics Set Up Time Before LE Rises Time Width of LE Clock Delay Time to Data Out Turn On Time Turn Off Time Time Width of CL Off Isolation Max Clock Freq Set Up Time Data to Clock Hold Time Data from Clock Switch Crosstalk Sym tSD tWLE tDO tON tOFF tWCL KO fCLK tSU th KCR 13-18 0 35 -45 5.0 10 150 -35 -45 3.0 0C min max min 260 300 250 2.5 5.0 330 5.0 10 5.0 10 +25C typ max +70C min max Units ns ns ns s s ns dB MHz ns ns dB Signal Freq. = 5MHz Signal Freq. = 5MHz 50% Duty Cycle fDATA = fCLK/2 RL =10K RL =10K Test Conditions HV1816 Operating Conditions Symbol VDD VPP VNN VIH VIL VSIG TA Parameter Logic power supply voltage Positive high voltage supply Negative high voltage supply High level input voltage Low-level input voltage Analog signal voltage peak to peak Operating free air-temperature Value +10.0V to +15.5V +50V to +80V -50V to -80V VDD -2V to VDD 0 to 2.0V VNN +15V to VPP -15V 0 to 70C Notes: 1. Power up/down sequence is arbitrary except GND must be powered-up first and powered-down last. 2. VSIG must be VNN VSIG VPP or floating during power up/down transition. Test Circuits VPP -15V ISOL VPP -15V VIN = 10 VP-P @5MHz VOUT RL VOUT 10K NC VNN +15V www..com 50 50 +80V -80V VPP VNN VDD GND 15V +80V -80V VPP VNN VDD GND 15V +80V -80V VPP VNN VDD GND 15V KCR = 20Log VOUT VIN Switch OFF Leakage Crosstalk TON/TOFF 13 VIN = 10 VP-P @5MHz VOUT VOUT RL 100K RL +80V -80V VPP VNN VDD GND 15V +80V -80V VPP VNN VDD GND 15V KO = 20Log VOUT VIN OFF Isolation DC Offset ON/OFF 13-19 HV1816 Logic Timing Waveforms DN - 1 DATA IN 50% DN 50% DN + 1 LE 50% 50% tWLE tSD 50% 50% th tDO CLOCK t SU DATA OUT 50% tOFF tON VOUT OFF (TYP) ON 90% 10% CLR 50% t WCL 50% www..com Logic Diagram LATCHES DIN D LE CL D LE CL D LE CL D LE CL D LE CL D LE CL D LE CL D LE CL LEVEL SHIFTERS OUTPUT SWITCHES SW0 CLK SW1 SW2 SW3 8 BIT SHIFT REGISTER SW4 SW5 DOUT SW6 SW7 VNN VPP VDD LE CL 13-20 HV1816 Truth Table D0 L H L H L H L H L H L H L H L H X X X X X X X X X X X X X X X X D1 D2 D3 D4 D5 D6 D7 LE L L L L L L L L L L L L L L L L X H CL L L L L L L L L L L L L L L L L H L OFF OFF OFF OFF OFF OFF OFF SW0 OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF SW1 SW2 SW3 SW4 SW5 SW6 SW7 HOLD PREVIOUS STATE www..com Notes: 1. The eight switches operate independently. 2. Serial data is clocked in on the L H transition CLK. 3. The clear input over rides all other inputs. 4. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift register data flows through the latch. 5. DOUT is high when switch 7 is on. 6. Shift register clocking has no effect on the switch states if LE is H. 13 13-21 HV1816 Pin Configurations 28-Pin DIP Pin Function 1 SW3 2 SW3 3 SW2 4 SW2 5 SW1 6 SW1 7 SW0 8 SW0 9 VPP 10 VNN 11 N/C 12 GND 13 VDD 14 N/C Pin 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Function N/C DIN CLK LE CL DOUT SW7 SW7 SW6 SW6 SW5 SW5 SW4 SW4 Package Outlines 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 top view 28-pin DIP 28-Pin J-Lead Pin Function 1 SW3 www..com 2 SW3 3 SW2 4 SW2 5 SW1 6 SW1 7 SW0 8 SW0 9 VPP 10 VNN 11 N/C 12 GND 13 VDD 14 N/C 25 24 23 22 21 20 19 18 17 16 15 14 13 12 Pin 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Function N/C DIN CLK LE CL DOUT SW7 SW7 SW6 SW6 SW5 SW5 SW4 SW4 26 27 28 1 2 3 4 5 6 7 8 9 10 11 top view 28-pin J-Lead Package 13-22 |
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